The following description will explain a conventional TFT (thin film transistor) -LCD (liquid crystal display) module, while referring to FIG. 40. Here, "module" refers to an independent unit which satisfies requirements such that only by combining a plurality of the modules, a grand system such as a TV set or a personal computer can be formed.
A TFT-LCD module 501 is equipped with a controller 510, a liquid crystal driving power source circuit 520, a gate driver group (gate electrode driving circuit) 530, a source driver group (source electrode driving circuit) 540, and a liquid crystal panel 550, as shown in FIG. 40.
According to a synchronization signal supplied from outside (from a host system), the controller 510 controls production of a scanning pulse by the gate driver group 530 and performs timing control of an Nbit display data signal and a driving control signal by the source driver group 540. The liquid crystal power source circuit 520 receives power from an external power source and supplies power to the gate driver group 530 and the source driver group 540, as well as to a common electrode.
The gate driver group 530 is composed of an "m" number of gate drivers G1 through Gm, and the gate drivers G1 through Gm are multi-output drivers for driving gate bus lines (a plurality of the same are provided horizontally as viewed in FIG. 41) of the liquid crystal panel 550, and are generally referred to as gate drivers. Each gate driver is, though not shown in the figure, composed of (1) films called as tape carriers made of copper film wires which are laid at fine intervals on an insulating film so as to connect input/output terminals of an LSI chip with electrodes of other constituent parts, respectively, and (2) sealing resin for fixing and dehumidifying the LSI chip.
Likewise, the source driver group 540 is composed of an "n" number of source drivers S1 through Sn. The source drivers SI through Sn are multi-output drivers for driving source bus lines (a plurality of the same are provided vertically as viewed in FIG. 41) of the liquid crystal panel 550, and are generally referred to as source drivers. Each source driver is, though not shown in the figure, composed of (1) films called as tape carriers made of copper film wires which are laid at fine intervals on an insulating film so as to connect input/output terminals of an LSI chip with electrodes of other constituent parts, respectively, and (2) sealing resin for fixing and dehumidifying the LSI chip.
The liquid crystal panel 550, as shown in FIG. 41, can be plotted into an equivalent circuit diagram of a TFT liquid crystal panel. In the liquid crystal panel 550, a plurality of TFTs are provided in a matrix form, and each TFT is connected with a display electrode which is formed so as to correspond to each pixel. Further, the common electrode is formed so as to face each display electrode. The common electrode is an electrode commonly corresponding to all the pixels.
When a positive voltage is applied to the gate electrode of the TFT (usually supplied from the gate driver), the TFT is turned on. In accordance with a voltage applied to the source bus line, a liquid crystal load capacitor formed between the display electrode and the common electrode is charged.
When a negative voltage is applied to the gate electrode, the TFT is turned off, and a voltage applied at the time is maintained by the liquid crystal load capacitor between the display electrode and the common electrode.
By controlling a gate voltage in a state in which an appropriate voltage is applied to the source electrode (usually supplied from the source driver), a desired voltage can be maintained by the pixel. Transmittance of the liquid crystal is varied in accordance with the voltage thus maintained, whereby images are displayed. To be more specific, as shown in FIG. 42, the liquid crystal whose transmittance has varied is backlighted, and light having passed through the liquid crystal is projected on color filters, whereby images are displayed.
The following description will explain the gate drivers G1 through Gm constituting the gate driver group 530, while referring to FIG. 43. Since the gate drivers G1 through Gm have the same arrangement, FIG. 43 is a schematic block diagram of one gate driver LSI chip.
The gate driver LSI chip is provided with a shift register circuit 561, a level shifter circuit 562, and an output circuit 563. The functions of the blocks will be explained below.
The shift register circuit 561 performs a shifting operation in accordance with a horizontal synchronization signal SPD in response to a vertical synchronization signal CLD, and outputs a selection pulse for selecting, from among the pixels of the liquid crystal panel, a pixel to be driven by a voltage outputted from the source driver group 540.
The level shifter circuit 562 shifts a level of the selection pulse to a voltage level required for turning on/off TFTs, and a signal thus converted is sent to the output circuit 563. The output circuit 563 amplifies the signal thus inputted thereto, by using an output buffer circuit installed therein, and outputs the amplified signal through an output terminal. Outputs OP1 through OPn from the output circuit 563 are signals in a pulse form, and are hereinafter referred to as gate pulses.
Signal timings of the vertical synchronization signal CLD, the horizontal synchronization signal SPD, and the outputs OP1 through OPn are shown in FIG. 44 which explains the present invention.
The following description will explain the source drivers S1 through Sn constituting the source driver group 540, while referring to FIG. 45. FIG. 45 is a schematic block diagram showing one of the source driver LSI chips which constitute the source drivers S1 through Sn, respectively. A block diagram of an arrangement for display with 64 scales of color gradation is shown here.
The source driver LSI chip is composed of a shift register circuit 571, an input latch circuit 572, a sampling memory circuit 573, a holding memory circuit 574, a reference voltage producing circuit 575, a DA converter circuit 576, and an output circuit 577. The functions of the blocks are explained below.
The shift register circuit 571 performs a shifting operation in response to a start pulse signal SPI of the source driver in accordance with an input clock signal CK, and selects a bit for sampling data. Here, a start pulse signal SPO (cascade output signal) is outputted from a final stage of the shift register circuit 571 to an LSI chip of the subsequent stage.
Therefore, the start pulse signal SPI is supplied from outside only to the source driver S1 among the source drivers S1 through Sn installed in the liquid crystal panel 550. Regarding each of the other source drivers, the cascade output signal SPO taken out of the final stage of the previous shift register circuit 571 is inputted as the start pulse signal. FIG. 46 shows an example of a liquid crystal panel 550 equipped with four source drivers.
The input latch circuit 572 temporarily latches an input display data signal DATA (6 bits per each of R, G, and B), and thereafter, sends it to the sampling memory circuit 573.
The sampling memory circuit 573 samples the data inputted thereto by time sharing and stores the data.
The hold memory circuit 574 latches the data (display data signal) stored in the sampling memory circuit 573 all together, in accordance with a signal LS inputted thereto.
The reference voltage producing circuit 575 generates voltages of 64 levels by resistance dividing, based on a reference voltage of a signal Vref.
The DA converter circuit 576 generates an analog signal in accordance with the display data signal, and sends the analog signal to the output circuit 577. The output circuit 577 amplifies the analog signal of 64 levels by using an output buffer circuit, and outputs the amplified result through an output terminal.
The source driver for display of 64 scales of color gradation can be explained as in the foregoing description.
FIG. 47 is a timing chart showing the signals of the source driver for display of 64 scales in the case where four source drivers are provided to the liquid crystal panel 550 as shown in FIG. 46.
Incidentally, as the resolution of the liquid crystal panel is further heightened (due to an increase in the number of dots provided in vertical and horizontal directions) and scales of color gradation thereof increase, the liquid crystal driver (source driver in this case) is recently more and more required to have a higher data transfer speed.
The data transfer speed (fxck) of the liquid crystal driver is found by the following formula: EQU fxck=Y.times.X.times.N.times.fFR/D/n (Hz)
where:
Y: number of dots in horizontal direction [(number of pixels in horizontal direction).times.3 (RGB)] PA1 X: number of dots in vertical direction [number of pixels in vertical direction] PA1 N: number of scale-use bits [2.sup.N scales] PA1 fFR: frame frequency [usually, about 70 Hz] PA1 D: number of data inputted [N.times.3 (RGB)] PA1 n: driving parameter [n=2 in the case of both-side driving, or n=1 in the case of one-side driving]
For example, assume that regarding a XGA-use liquid color panel of 1024.times.768 size, the number N of scale-use bits, the frame frequency fFR, and the number of inputted data are set to 64 (N=6), 70Hz, and 18 bits, respectively, and the unilateral driving is performed. In this case, the data transfer frequency required of the source driver is: EQU (1024.times.3.times.768.times.6.times.70).div.18=55 MHz
Table 1 below shows data transfer speeds of the source drivers of various pixel size specifications (calculated in the aforementioned manner).
TABLE 1 DATA TRANSFER SPEED SPECIFICATION NUMBER OF DOTS OF SOURCE DRIVER SVGA 800 .times. 600 - 35 MHz - XGA 1024 .times. 768 - 55 MHz - SXGA 1280 .times. 1024 - 95 MHz -
However, regarding the TFT-LCD module, it has been known to those skilled in the art that EMI noise is a great problem with respect to a high data transfer speed which such high resolution specification as above requires, and various enterprises have so far examined and attempted various schemes to solve the problem.
For example, to suppress the EMI noise, a small amplitude differential signal transmitting scheme has conventionally been applied to a driving circuit of a liquid crystal display device.
The small amplitude differential signal transmitting scheme is a scheme as shown in FIG. 48. In a TFT-LCD module 502, a signal from the controller 510 is sent to a source driver group 540 with a small amplitude, and the signal thus transmitted to the source driver group 540 is first received by a comparator circuit group of a differential amplifier type before being transmitted to a circuit on the subsequent stage or the like. More specifically, it is generally said that a radiation level of the EMI noise is proportional to a square of a voltage of a signal line and the number of signal lines. The small amplitude differential signal transmitting scheme uses a differential signal with an extremely small amplitude, and hence, it is regarded as one of schemes which ensure reduction of the EMI.
Here, the small amplitude differential signal transmitting scheme will be explained in the following description.
FIG. 48 shows an example of the TFT-LCD module 502 of the small amplitude differential signal transmitting scheme. The TFT-LCD module 502 differs from the TFT-LCD module 501 shown in FIG. 40, in the following aspect: in the TFT-LCD module 502, lines through which the display data signal DATA (R, G, B .times.Nbit) and the input clock signal CK are supplied from the controller 510 to the source driver group 540 are doubled, as compared to the TFT-LCD module 501.
The reason why the input lines from the controller 510 to the source driver group 540 are doubled is, though it will be explained in detail later, as follows. Twisted signals with small amplitudes are supplied to an interface circuit 600 (see FIG. 49) installed in each source driver, and they are compared by comparator circuits of a differential amplifier type, each of which has two input terminals for non-inverting input (+) and inverting input (-). Thereafter, compared results are converted to signals with great amplitudes, and the signals are supplied to internal circuits at the subsequent stage. Incidentally, according to the small amplitude differential signal transmitting scheme, even a level of an input signal with an extremely small amplitude can be changed by a differential amplifier, but there are the following drawbacks: the number of input terminals increases by at least two per one output circuit, and consumed power increases since a response speed of the differential amplifier has to be raised by flowing much current through a constant power supply source of the differential amplifier. More specifically, in the case where the small amplitude differential signal transmitting scheme is applied, current necessary for the constant power source of the differential amplifier becomes several tens .mu.A, which is one order higher than that for a usual comparator circuit.
FIG. 49 is a block diagram of a source driver constituting the source driver group 540 of the TFT-LCD module 502. Here, a circuit block diagram of a source driver LSI chip constituting one among the source driver S.sub.1 through S.sub.n is shown.
The foregoing source driver LSI chip greatly differs from the driver LSI chip shown in FIG. 45 in the following aspect: in the case of the former, the input clock signal and the input display data signals are supplied through the interface circuit 600. Incidentally, as described above, the number of input lines for the display data signals and the number of input terminals for the input clock signals are doubled, respectively, as compared with those of the source driver LSI chip shown in FIG. 45.
FIG. 50(b) shows an arrangement example of the interface circuit 600. The interface circuit 600 is composed of a plurality of comparators 601 each of which is a differential amplifier-type comparator with two input terminals for non-inverting input (+) and inverting input (-) and one output terminal. More specifically, as shown in FIG. 50(a), regarding each pair of the input terminals CK and DATA for the clock signal and the display data signals in the interface circuit 600, small-amplitude pulse signals of 1.0 V to 1.4 V in a twisted state are supplied to the input terminals for the non-inverting input (+) and the inverting input (-), respectively. The pulse signals are compared by the comparators 601, and then, their levels are shifted. Thereafter, as shown in FIG. 50(c), pulse signals of 0 V to 3 V are outputted by setting the power source voltages VCC of the comparators 601 to 3V, the same level of that of the source driver LSI chip.
Each comparator 601 is equipped with, for example, a comparing circuit 601 a and a source follower circuit 601b, as shown in FIG. 51. In the case where a P-channel transistor and an N-channel transistor provided in the comparator 601 as described above are replaced with each other, it results in a comparator 602 equipped with a comparing circuit 602a and a source follower circuit 602b as shown in FIG. 52.
Incidentally, to narrow a frame part of the liquid crystal module, a scheme wherein liquid crystal drivers (drivers for driving the source bus line side) are provided on both upper and lower sides of the liquid crystal panel so that the liquid crystal panel is driven from both the sides has recently been substituted by a scheme wherein the liquid crystal drivers are provided on one side of the liquid crystal panel so as to drive the liquid crystal panel, and therefore, twice the conventional transfer speed of the liquid crystal drivers has been required.
Besides, the number of pixels has been rapidly changed, from that of VGA to that of SVGA, and further, shift to XGA, and to SXGA has started. This entails a rapid increase in a necessary driving frequency.
However, as described above, in the case where a high-speed pulse signal is dealt with, the EMI noise is a serious problem. As a typical scheme to reduce the EMI noise, the aforementioned small amplitude differential signal transmitting scheme is well-known.
The small amplitude differential signal transmitting scheme which has been conventionally conducted, however, requires two differential input terminals per one bit. For example, in a 64-scale source driver, 18 (6 bits.times.3 (RGB)) data input lines have conventionally been needed, but in the case of the small amplitude differential signal transmitting scheme, twice the number in the conventional case, that is, 36 (6 bit.times.3 (RGB).times.2), of display data input lines are needed. Further, in the case of 256 scales, no less than 48 (8 bit.times.3 (RGB).times.2) display data input lines are necessary.
Such an increase in the number of display data input lines causes many problems to manufacturers and assemblers.
The problems include expansion of a size of the LSI chip which entails a rise of costs, a decline of a yield of the LSI chip, degradation of reliability stemming from an increase in the number of the input terminals, expansion of a size of TCP (tape carrier package) which entails a rise of costs, a decline of the yield due to the TCP assembling process, expansion of an input lines substrate of the TFT-LCD module which entails expansion of a frame thereof.